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Altera_Forum
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18 years ago

change logic cell to memory M4K in cylocne 2

How I can say to Quartus 2 (7.2), to replace logic cells to memory blocks M4K in Cyclone 2 device? I would like to implement following array with memory M4K and not LC type CoefArrType is arra...
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Altera_Forum
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18 years ago

Hello,

it's clear to me, that in this case coefarr can't be inferred as internal RAM, cause the array elements are accessed simultanously. RAM storage locations can only be accessed sequentially, one address each clock cycle. E. g. with fast FIR filters, where all coefficients must be accessed each clock cycle, RAM can't be used. You can consult the Altera FIR compiler manual or evaluate by creating a filter design for trial, how Altera FIR filter tools manages coefficient storage.

Regards,

Frank