change logic cell to memory M4K in cylocne 2

Thanx a lot for replay. This code is generated by Synplicity DSP...

Below is example of accessing to signal multBufs1.

CoefArr <= CoefArrTemp;

multInp <= signed(inp);

rstBuf <= '0';

enBuf <= '1';

outp <= std_logic_vector(sumOut);

floop: for i in 1 to tapLen-1 generate

multBufs1(i) <= syn_resize(Shift_Right(mem(i*4-1) * CoefArr(i),

(coefFrac+inpFrac-dpFrac)), dpBitWidth);

end generate;

multBufs1(0) <= syn_resize(Shift_Right(multInp * CoefArr(0),

(coefFrac+inpFrac-dpFrac)), dpBitWidth);

gloop: for i in 0 to numfourAdders-1 generate

sumFLOuts(i) <= signed(syn_resize(multBufs1(i*4) +multBufs1(i*4+1)+multBufs1(i*4+2)+multBufs1(i*4+3), outBitWidth));

sumFLOutsDelayed(i) <= signed(sumFLOuts(i));

end generate;

sumFLOuts(numfourAdders) <= multBufs1(numfourAdders*4) ;

sumFLOutsDelayed(25) <= signed(sumFLOuts(25));

sumOut <= sumFLOutsDelayed(0) + sumFLOutsDelayed(1) + sumFLOutsDelayed(2) + sumFLOutsDelayed(3) + sumFLOutsDelayed(4) + sumFLOutsDelayed(5) + sumFLOutsDelayed(6) + sumFLOutsDelayed(7) + sumFLOutsDelayed(8) + sumFLOutsDelayed(9) + sumFLOutsDelayed(10) + sumFLOutsDelayed(11) + sumFLOutsDelayed(12) + sumFLOutsDelayed(13) + sumFLOutsDelayed(14) + sumFLOutsDelayed(15) + sumFLOutsDelayed(16) + sumFLOutsDelayed(17) + sumFLOutsDelayed(18) + sumFLOutsDelayed(19) + sumFLOutsDelayed(20) + sumFLOutsDelayed(21) + sumFLOutsDelayed(22) + sumFLOutsDelayed(23) + sumFLOutsDelayed(24) + sumFLOutsDelayed(25);