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Altera_Forum's avatar
Altera_Forum
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18 years ago

change logic cell to memory M4K in cylocne 2

How I can say to Quartus 2 (7.2), to replace logic cells to memory blocks M4K in Cyclone 2 device? I would like to implement following array with memory M4K and not LC type CoefArrType is arra...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

I wonder how you achieved to make Quartus use LC for a the signal array? Most likely you have multiple accesses to the signal in your code or are assigning the address expression outside a clock synchronous process. You should consider the limitations of internal RAM hardware.