Capturing data from Marvell 88E1111 PHY of Arria II GX FPGA Development Board.

Hi,

I am trying to getting data from Marvell 88E1111 PHY of Arria II GX FPGA Development Board, but I can't capture anything on SignalTap. Anybody could help me?

I linked the data that come from Marvell 88E1111 PHY to Arria II GX using following FPGA pins:

RGMII receive data ENET_RX_D[0] E21

RGMII receive data ENET_RX_D[1] E24

RGMII receive data ENET_RX_D[2] E22

RGMII receive data ENET_RX_D[3] F24

The project is clocked using 125MHz internal clock. (I am using PLL M=1 D=1).

Just for test, these data is being registred and output to following pins:

USR_LED0 G1

USR_LED1 J4

USR_LED2 J5

USR_LED3 R5

The code is

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_unsigned.all;

USE IEEE.STD_LOGIC_ARITH.ALL;

entity gige is

port (

i_Clk : in std_logic;

i_Clk_Eth : in std_logic;

i_Rst : in std_logic;--// Active in High

i_RX_Data : in std_logic_vector(3 downto 0);

i_RX_DV : in std_logic;

o_Data : out std_logic_vector(3 downto 0);

o_RstEth : out std_logic

);

end gige;

architecture Behavioral of gige is

component pll

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

end component;

signal s_clk_125 : std_logic;

signal s_RstPLL : std_logic;

begin

Inst_pll : pll

port map (

inclk0 => i_Clk,

areset => s_RstPLL,

c0 => s_clk_125,

--c1 => s_clk_62_5,

locked => open--s_locked

);

s_RstPLL <= not(i_Rst);

process(s_clk_125, i_Rst)

begin

if (i_Rst = '0') then

o_RstEth <= '0';

o_Data <= (others => '0');

elsif rising_edge(s_clk_125) then

o_RstEth <= i_Rst;

o_Data <= i_RX_Data;

end if;

end process;

end Behavioral;