Can you provide more details on the SEU testing results performed by Intel ? (https://www.intel.com/content/www/us/en/programmable/support/quality-and-reliability/seu.html)

Hi,

- Can you provide details on the test procedures you have performed (JESD-89) ?

The method we use to performed the testing is by bringing our board with the FPGA into the JESD-89 compliance lab and have the external factor such alpha particle to attack the FPGA device and observed the SEU.

- Can you provide numerical data - or some sort of report of your testing ?

Please refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/rr/rr.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=altera&_ga=2.6507250.1501909099.1553290013-1866113875.1553290013 for all the FPGA device reliability result.

- Can you elaborate on the statement to the error detection capability of the CRC circuit ?

For each Quartus design compilation bitstream will contain pre-computed CRC signature which will be compare to the readback stream of the CRAM bit which we will used to detect if there is any error and calculate how many bit error does occurs.

Are you referencing to all multi bit errors you observed during testing, or to all possible multi bit errors ?

The device will only flag if it is a single bit error or multiple bit error.