Can you provide more detail of the SEU vulnerabilities for the Cyclone 10 GX?

Hi,

The SEU is tested on the CRAM bit and it is tested across supported temperature and speed grade.

Please refer to Cyclone 10 GX SEU Mitigation (https://www.intel.com/content/www/us/en/programmable/documentation/vua1487061384661.html#sam1403483263288) on the FIT calculation. The FPGA was tested with using external particle to attack the FPGA CRAM bit to see how easy it is flip and impact the functionality of the design.

There is no way to check the MLAB memory issue unless you create your own ECC to make sure that the SEU is not happening.

The mitigation is only targeting for CRAM bit and functionality. For the FPGA memories, we recommend user to use ECC to handle the RAM corruption