can MAX10 FPGA part “10M50DAF672I7G" support LVCMOS 1V standard

Hi,

You need to refer to this User Guide from the link below:

https://www.intel.com/content/www/us/en/docs/programmable/683751/22-1/guidelines-placement-restrictions-for.html

You need to ensure that the total mutual inductance (Lm) of the I/O pins in usage surrounding the 1.0 V I/O does not exceed the guidelines.

Regards,

Aqid