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vlata's avatar
vlata
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2 years ago

can MAX10 FPGA part “10M50DAF672I7G" support LVCMOS 1V standard

We have used MAX10 FPGA part “10M50DAF672I7G" for one board and we need to connect the FPGA GPIO with LVCMOS 1V interface. As per datasheet it is mentioned that this series will support the LVCMOS 1...
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vlata's avatar
vlata
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2 years ago

Thank you for supporting We are using 20.1.1. Is it due to version?

FvM's avatar
FvM
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2 years ago
Hi,
you may have noticed that the same question was asked shortly before.
The answer is in the other thread, yes it's a version problem.
  • vlata's avatar
    vlata
    Icon for New Contributor rankNew Contributor
    2 years ago

    We have run in Quartus 22.1 version now error is not showing for BANK 4 to BANK 7 regarding LVCMOS 1v gpio but some critical warnings are showing on total mutual inductance. Please refer to the critical warning message below.

    Critical Warning (21688): The total mutual inductance (Lm) of 1.0 V I/O pin R24 with surrounding 1.0 V I/O pins is 7.446000 nH. This is not allowed. The total mutual inductance must be less than or equal to 7.41 nH

    Can you please help us why these warning is showing , these banks will support LVCMOS 1v or Not?