Forum Discussion

Occasional Contributor

6 years ago

Can LVDS clock pin be assigned to general differential IO?

Hi experts, We are using LVDS with internal PLL, on 10M50 board. Is there a hard requirement that LVDS tx/rx clock pin should be assigned to a dedicate clock pin? Is there any violations or bad im...

SreekumarR_G_Intel

Frequent Contributor

6 years ago

Looks like Pin V9 and V10 is dedicated clk input , whereas W5 and W6 is not . PLL inclk should be from the dedicated clk pin.

You can try to use the altclkbuf cntrl ip option. This might help to connect the non-dedicated input clk pin to clk tree in the FPGA.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_altclock.pdf

Thanks

Forum Discussion

Can LVDS clock pin be assigned to general differential IO?

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