Open Side Menu
Skip to contentBrand Logo
Forums
BlogKnowledge BaseAltera.com
RegisterSign In
  1. Altera Community
  2. Forums
  3. Boards & Dev Kits

Forum Discussion

TGao's avatar
TGao
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

C10LP的电源纹波和IO极限电流

Hi 您好, 请问C10LP的电源纹波和IO极限电流 是多少 Ted.Gao
YuanLi_S_Intel's avatar
YuanLi_S_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

你好,你可以参考以下的datasheet。​

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/c10lp-51002.pdf (Page 4)

Recent Discussions

  • Thulasi's avatar
    Agilex™ 7 FPGA M-Series Development Kit_HBM2e Edition_REVB2_Altera
    2 days ago
    Thulasi
  • Dexter22's avatar
    Agilex 7 R-Tile PIPE Direct endpoint receives Set_Slot_Power_Limit, but no Config TLPs
    2 days ago
    Dexter22
  • Thulasi's avatar
    SyncE clock as the reference for DDR, HBM, and FPGA control interfaces in the Agilex M-Series design
    3 days ago
    Thulasi
  • zw_lee's avatar
    R-tile CXL base hard IP example for the Agilex 7 M-series Dev Kit (DK_DEV_AGM039EA) does not work
    3 days ago
    zw_lee
  • hmitani's avatar
    PCIe Root Complex on DK-A5E013BM16AEA
    3 days ago
    hmitani
Contact Us
Altera YoutubeAltera YoutubeAltera Twitter
  • Company Overview
  • Newsroom
  • Our Leaders
  • Careers
Subscribe to Altera Newsletter

© Altera Corporation | Terms of Use | Privacy Policy | Cookies | Trademarks | PSIRT

Altera Logo