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GuilleJake's avatar
GuilleJake
Icon for New Contributor rankNew Contributor
4 years ago
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BURST ACCESS with UNIPHY DDR-FPGA and DDR-HPS memory controller in CYCLONE V, using QUARTUS Prime 18

WRITE BURSTS Since the beginbursttransfer signal no longer exists, if you want to concatenate successive write bursts: Q: is it necessary to enter a dead cycle with write=0 at the end of each bur...
  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    4 years ago

    Hi GuilleJake,

    The controller can identify the burst operation from user's command.

    When user assert the address, burstcount, read or write and data, the controller knows that the user want to do the burst operation starting at the address with the burstcount value.

    So when there is a burst signal such as burstcount, the controller will know that this is a burst operation.

    Then the controller will act accordingly to do the burst operation.

    They do not need the beginbursttransfer signal to start the operation because the controller is smart enough to identify the operation.

    Thanks,

    Adzim

AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi GuilleJack,


I'm Adzim. Thanks for using Intel Community.


Yes you are right about the beginbursttransfer signal.

The beginbursttransfer signal exists to support the legacy memory controllers as stated in the Avalon Interface Specification at page 17.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_avalon_spec.pdf


There are a lot of information regarding to your question that contain inside the Avalon document.

You should refer to the link above in chapter 3.5 about the read and write transfer processes.


For the maximum burstcount, you should count it with the formula 2^(N-1) where N is width size.

The width should be 1 - 11.


Regards,

Adzim