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MYuan2's avatar
MYuan2
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6 years ago

Both CPU0 and CPU1 found on 5CSEBA5U23I7S (which supposed to be a single core)

We use cyclone V 5CSEBA5U2317S for a long time and we are sure it has a single core in MPU, it can be confirmed by cat /proc/cpuinfo (shows only cpu0) and register 0xFFD08018 (bit 0 indicates that cp...
sstrell's avatar
sstrell
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6 years ago

I've been working with these devices for 6 years and never knew there was a single core option. I guess CPU1 is simply not available in devices with the S code. Is your question that you have newer S code devices that now show both cores available?

#iwork4intel

MYuan2's avatar
MYuan2
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6 years ago

Yeh exactly ... all the older S devices (bought more than 2 years ago) we got here has only CPU 0 core but the most recent S devices we bought shows CPU0 and CPU1 are all there. I am also confused because we have been using this single core FPGA since 2014 because it is much cheaper than the dual core. The only difference we can see on the chip is that the dual core FPGAs are made in Taiwan while the single core FPGAs are made in Korea....

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Correct me if I am wrong, the newly ordered 5CSEBA5U23I7S(which is a single core) devices shows both cores available (CPU0 and CPU1)?

    But the old 5CSEBA5U23I7S devices that you have owned, shows only one core available(CPU0)?

    May I know if you are you facing any booting issues with this?

  • MYuan2's avatar
    MYuan2
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    6 years ago

    Yes you are right.

    I don't have booting issue with 2 cores available.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    Thanks for the information, I will check with our internal team regarding this issue.

    Is it possible for you to share the screenshot of the "LSB of sysmgr register (0xFFD08000) we can see cpu 1 is not available (bit set to 0) in MPU", for both old and new devices?

    Thanks.

  • MYuan2's avatar
    MYuan2
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    6 years ago

  • MYuan2's avatar
    MYuan2
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    6 years ago

    Sorry the address 0xFFD08000 is not right. I forgot to mention the offset. The correct address is 0xFFD08018 which is shown in picture above.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    HI,

    Thanks for the screenshot, I will check with our internal team regarding this issue.

    Regards.

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I would like to know if all your questions have been answered.

    "Is there any pin on HPS that can block CPU1 or does Intel give an extra core for free on Cyclone V?"

    -> Are you using Linux? You can disable the cpu 1 (even though it is not available) by root:

    echo 0 > /sys/devices/system/cpu/cpu1/online

    Hope this helps.

  • MYuan2's avatar
    MYuan2
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    We are using Linux and actually we are doing this <echo 0 > /sys/devices/system/cpu/cpu1/online> to disable CPU1.

    But what we are more interested in is why the two FPGAs we bought are different even serial numbers are the same.

    And do we still get 2 cores with 5CSEBA5U23I7S FPGAs in the future? Because we are going to buy more.

    If so, can we use the second core safely?

  • EBERLAZARE_I_Intel's avatar
    EBERLAZARE_I_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago

    Hi,

    I am still waiting for internal team to reply, can you specify how many board are involved/affected?

  • MYuan2's avatar
    MYuan2
    Icon for New Contributor rankNew Contributor
    6 years ago

    We bought at least three hundreds of 5CSEBA5U23I7S (both old and new) and we are going to buy more. So far we checked around 50 of them. All older ones has single core and newer ones have due core.