Forum Discussion
Altera_Forum
Honored Contributor
10 years agoBuilt-in USB Blaster use MAX V CPLD and FTDI chip. You could check if CPLD is fine with JTAG header (unpopulated).
You can use Test Point TP10,TP11,TP12,TP13 to access JTAG interface of FPGA and check if it is working. See schematic. Bye