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I've tried that, non of them are configured to be output, all inputs...
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Your original question did not mention you cared about the direction. That would be a function of the SOPC system.
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Which means i cant really use NIOS2 design... such a nicely designed FPGA, what a waste.:(
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Yep, I agree that it was a bad choice to select a memory that was not directly supported by Altera's IP.
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Tried that too.. they will only allow you to use it for 1 hour everytime you compile.
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That is a pain.
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I would much rather get a Terasic DE0-nano than Bemicro Nano, since they provide important IP cores. I found out, i could actually use the SDRAM controller that comes with SOPC builder, just a little timing configuration.
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The Terasic boards are all good.
Cheers,
Dave
Honored Contributor
