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Hi,
Was anyone able to get through the FPGA compilation of the Arrow lab on the "BeMicro Embedded System Lab"? I got to page 36, the part where the FPGA programming code is generated and got the message:
Error: Can't generate netlist output files because the file C:/altera/kits/bemicro/bemicro_sopc_builder_lab/incremental_db/compiled_partitions/bemicro_lab_schem.root_partition.map.atm" is an OpenCore Plus time-limited file
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I did not get any error like this. It was telling me during download that i need the time limited but thats because of the NIOS is not licenced (Quartus 2 web edition)
Until i dont hit cancel on that "open core plus" window, it works correctly for me.
Honored Contributor
