Forum Discussion
Altera_Forum
Honored Contributor
14 years agoThere are two simple ways to load the SFL IP to your FPGA to access the serial flash through indirect JTAG programming.
- load the default factory image shipped with Quartus sfl_ep3c16.sof - instantiate the SFL IP in your design after generating the code in MegaWizardsfl_inst : sfl PORT MAP (
noe_in => '0'
); You additionally need to convert the configuration stream to *.jic with the Quartus conversion tool.