Beginners question: Debugging a FPGA design on an Altera Board

The easiest way to do this is to build a component with an AXI master and an AXI slave, you can use the debug.driven_by property to link the ports together so you don't need any HDL. A simple example in the 13.1 library is altera_clock_bridge (ip/altera/merlin/altera_clock_bridge/altera_clock_bridge_hw.tcl)

Once you have such a component you can use it to constrain the memory mapped port to be the correct shape for your component - you can put it into your system in place of the Avalon MM bridge in your post above and export its master interface.