Beginners question: Debugging a FPGA design on an Altera Board

Hi there,

I'm about to implement my design in Qsys. So far I like this tool, but after some succesfull playing-around, I'm now stuck with a problem I can't figure out.

First let me explain, what I wanna do:

Our company has developed an ASIC with several highspeed interfaces. In order to test these interfaces we want to use a FPGA board. This board will contain one of those interfaces which we will connect to the ASIC. So the configuration looks like this

PC (with Qsys) <=> USB cable <=> USB Blaster II <=> USB Debug Master <=> Avalon <=> AXI Master <=> Interface with AXI Slave <=> ASIC

I want to simulate the design with Qsys (register accesses to the interface etc.). Therefore I have turned the interface into a Qsys component. This went pretty well.

But now I'm at the point where I need to connect the USB Debug Master with the AXI interface of my component. And I can't figure out, how to do this. As far as I see this, I need something that converts the Avalon protocol from the USB Debug Master into AXI master signals which I can connect to my AXI slave interface.

I looked at every AXI component available in Qsys but there is nothing that fits my requirements. I also checked this board and the Altera Support but I could not find an answer. The AXI Slave Agent which provides an AXI master interface has some streaming ports I don't now how to handle. The Qsys Interconnect manual mentions the Memory Burst Adapter without getting too specific. It's quite a puzzler.

Does anyone have experience with this issue? I'm pretty sure I'm not the first one trying to create an AXI connection in Qsys.