AXI Streaming Intel FPGA IP for PCI Express design example failing simulation

Hi Nick_kb,

Thanks for reaching out.

According to the user guide, the SR-IOV and Performance design examples are not supported in this release. Ignore the selections for these design examples in the IP Parameter Editor. The current version of the AXI Streaming FPGA IP only supports the PIO design example. Therefore, please try the PIO design example.

Additionally, please note that you are using an F-tile device, but the AXI Streaming Intel FPGA IP for PCI Express currently supports only Agilex 7 devices with R-Tile.

Regarding the simulator, please use the simulators supported on the PIO design example (VCS, VCSMX, Questasim, and Modelsim). In addition, the supported IP configurations are Gen5 1x16/2x8. For more details, please refer to Table 4 and Table 5.

Kindly refer to the user guide below.

AXI Streaming Intel® FPGA IP for PCI Express* User Guide (24.3.1 latest): https://www.intel.com/content/www/us/en/docs/programmable/790711/24-3-1/supported-features.html

Thanks.

Best Regards,

Ven