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Tirupataiah's avatar
Tirupataiah
Icon for New Contributor rankNew Contributor
2 years ago

AXI Bridge test in Stratix-10 EVM

Hi, I am unable to test the HPS->FPGA AXI bridge in Stratix-10 H-Tile Dev Kit. Please provide the reference example or document to test the HPS->FPGA AXI bridge in the Stratix-10 Dev Kit. Thank you...
Fpga Devkit
tehjingy_Altera's avatar
tehjingy_Altera
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi Tirupataiah

Once booted into linux, you could read or write to the memory location with the md command.

You could refer to the link below for the register map.

https://www.intel.com/content/www/us/en/programmable/hps/stratix-10/hps.html

To communicate through the HPS-to-FPGA bridge.

You can start write/read from the base address of 0xC0000000.

For the device that is connected to the bridge that you would like to interact with you could find the offset from the platform designer.

You could refer to the base column.

Please ignore the other IPs, the photo below serves the purpose of showing where the base address is.

Regards

Jingyang, Teh