AXE5-Falcon using the J8/J9 MIPI connectors?

Good questions — let me address both parts separately.
MIPI Reference Design for AXE5-Falcon J8/J9
The available documentation doesn't include a dedicated MIPI reference design specifically for the AXE5-Falcon board's J8/J9 MIPI connectors. Worth noting: in the context of the Agilex 5 E-Series 065B Premium Development Kit, J8 is documented as an HSIO bank SMA connector for 1PPS_OUT2 (or LVDS_SMA_TXP) Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide and J9 is an HVIO bank IO header (10-pins) Agilex™ 5 FPGA E-Series 065B Premium Development Kit User Guide — so the connector assignments in the available user guide material are specific to the Premium Dev Kit, not the AXE5-Falcon form factor. I'd point you to Altera's Example Design Hub (referenced in the kit product briefs) as the best place to check for published MIPI design examples.
RZQ_GROUP Error with B2A Differential Ref Clock / DP58 (RZQ_B_2A)
The root cause here is a pin-function conflict. The RZQ pin (in your case DP58/RZQ_B_2A) is a dedicated OCT calibration reference pin for its I/O bank. Quartus enforces an RZQ_GROUP rule that prevents this pin from being assigned to any other function — including use as a differential reference clock input — because doing so would break the OCT calibration for the entire bank group. You essentially cannot use RZQ_B_2A as your B2A differential reference clock pin.
For the GTS transceiver reference clock, there are two types of clock lines in the reference clock network — local and regional — and for every GTS transceiver bank there are two independent differential reference clock input pins. Reference Clock Network You need to assign your reference clock to one of those dedicated differential refclk pins in the GTS transceiver bank, not to the RZQ pin.
Additionally, on the same side as the GTS transceiver bank there is an HVIO bank, and there are single-ended input reference clock pins in that HVIO bank that can be used by the system PLL as a secondary option for the reference clock input source. Reference Clock Network
The fix is to re-assign your differential reference clock to a proper local or regional refclk pin for the GTS bank, or one of the dedicated HVIO SYSPLLREFCLK pins, and leave DP58/RZQ_B_2A unassigned (or assigned only to OCT). Check the Agilex 5 device pin-out files to identify the correct refclk-capable pin in the B2A bank area.