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ZhiqiangLiang's avatar
ZhiqiangLiang
Icon for Occasional Contributor rankOccasional Contributor
6 months ago

Avalon-MM Clock Crossing Bridge parameters setting

Hi, My FPGA model is Cyclone 10 LP 10CL120YF484. on Platform Designer, NIOS frequency is 80MHz, and my IP is 160MHz. In NIOS C code, I would like to read/write registers of my IP. In my design, ...
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ShengN_altera's avatar
ShengN_altera
Icon for Super Contributor rankSuper Contributor
6 months ago

Hi,


what do those parameters mean in Avalon-MM Clock Crossing Bridge setting?

You may check this https://www.intel.com/content/www/us/en/docs/programmable/683609/21-3/memory-mapped-clock-crossing-bridge-71915.html for definition

I think FOZDEMIR had explained most of them


in my design(NIOS 80MHz, IP 160MHz), how to set those parameters?

If you mean the frequecy parameter? As mentioned, just connect in between master and slave then it'll auto adapt the CDC


If no parameters can make my design work, what NIOS frequency should I set?

For this you may need to open a thread in Embedded forum for further confirmation.


Thanks,

Regards,

Sheng