Forum Discussion
New ContributorArria10 unpowered state issue
Hello,
Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.
We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.
Thank you.
Amin
Regular ContributorHello,
Intel Cyclone 10 GX, Intel Arria 10, and Intel Stratix 10 L-tile and H-tile device transceiver pins do not support ‘Hot-Socketing.’ Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins.
We would advise not to do that in unpowered state. The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices.
Thank you.
Amin
GlenHi,
In section 1.3.2 "Transceiver Pin Guidance for Unpowered FPGA" of AN 692 (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf)
It says:
"Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins."
We have several A10 boards inter-connected throuth XCVR (Serial Lite III). They are not powered on at the same time. XCVR pins of early powered devices may drive signals to unpowered XCVR pins of late powered devices. Will this lead to device damage? Thanks!
Best regards,
Glen
