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vivekt
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5 years ago

ARRIA10 GX-DDR4

I am designing a board with Arria10GX with DDR4 module. The input DDR4 Ref clock for the FPGA is LVDS (133.33MHZ) and is generated by a clock generator . However the pinout provided by the RTL...
vivekt's avatar
vivekt
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5 years ago

One more query regarding the Clock . If we look at the reference design for Bank 2I they have mentioned use OCT(an remove the 100R termination) , while for the bank 2K (DDR Bank) they do not want to use OCT. Is there any specific reason why we should not use OCT for DDR Bank