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vivekt's avatar
vivekt
Icon for New Contributor rankNew Contributor
5 years ago

ARRIA10 GX-DDR4

I am designing a board with Arria10GX with DDR4 module. The input DDR4 Ref clock for the FPGA is LVDS (133.33MHZ) and is generated by a clock generator . However the pinout provided by the RTL...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
5 years ago

VCCPT is connected to 1.8V in the schematic. So, as per the link that I shared earlier, LVDS signal can be connected to it.


Regards