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vivekt
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5 years ago

ARRIA10 GX-DDR4

I am designing a board with Arria10GX with DDR4 module. The input DDR4 Ref clock for the FPGA is LVDS (133.33MHZ) and is generated by a clock generator . However the pinout provided by the RTL...
vivekt's avatar
vivekt
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5 years ago

My query is regarding the input DDR Clock to the FPGA present in Bank 2K and not the connector side.

As per the schematic the Voltage connected to Bank2k is A10_VCCIO_MEM -(supporting voltages 1.2V/1.25V,1.35V,1.5V )

In the design nets CLK_EMI_P/CLK_EMI_N are used to generate LVDS clock of 133.33MHz for DDR Bank2K .

Attached image from reference design(Arria 10 GX FPGA Development Kit)