New Contributor
Regular ContributorHi JOter,
In the design, the output delay is set to only OUTPUT[0]. May I know what are the both signals mentioned? What is the signals that are not ok as there is no violation in the design?
Thanks.
New ContributorHi,
Thank you for your answer. I didn't see it until now, because a was waiting it in the support panel instead of "Comunity" panel.
In reference to your question the signal are: RAM_CLK (CLK) and OUTPUT 0 (counter)
We tested both signal in one scope, and we didn't notice any change between them changing the OUTPUT_DELAY constraints.
Remenber we checked it also using a C III, and in this case we got the spected signal.
We used the next constrains commands:
set_output_delay -clock vt_RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]
set_output_delay -clock vt_RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]
And
set_output_delay -clock RAM_CLK -max [expr $RAM_tsetup + $RAM_BDb_max - $RAM_CLK_DLY_MIN] [get_ports {OUTPUT[0]}]
set_output_delay -clock RAM_CLK -min [expr -$RAM_thold + $RAM_BDb_min - $RAM_CLK_DLY_MAX] [get_ports {OUTPUT[0]}]
Best regards
