Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Arria II GX Dev Kit - Ethernet RGMII

Hi I am new to FPGA world and thanks for the time. I am trying to run following reference design in lookback mode. http://www.alterawiki.com/wiki/triple_speed_ethernet_with_rgmii_in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

I am using Quartus 10 sp1.

I found the issue. There is a clock shift for Tx_clk and Rx_Clk in PHY.

I changed the Clock to 90 degree shift and every thing is working fine.

Thanks for the help.