Forum Discussion
New ContributorArria 10 SoC Development Kit: Not able to run Intel FPGA AI Suite Soc Design Example
Hi Rajan,
Our factory apps team gotten back to me on this case and mentioned that the latest Arria 10 SoC rev E. boards have a slower SDRAM (BOM change) and they have already change the design example in 2024.1 AI FPGA Suite to be able to accommodate these boards as well as the previous versions of the FPGA AI Suite do not work on A10 SoC rev. E boards.
Could you try on the design example in 2024.1 AI FPGA Suite?
Thanks
Regards
Kian
Frequent ContributorHi Rajan,
I apologize for the delay in response, was in offsite training for 3 days. Anyway I'm glad that you found the issue of the HPS memory IO not configured correctly. I've setup a system with fpga ai suite with one Arria 10 SOC devkit and also observed the SDRAM calibration failed. I will put a note to our guys to check whether example design needs to be updated.
As for the new issues observed DLA timeout when running interference, just want to confirm whether you have gone through the steps in (https://www.intel.com/content/www/us/en/docs/programmable/768979/2023-3/soc-design-example-user-guide.html) pg14 starting 3.5. Preparing the Intel Arria 10 SX SoC FPGA Development Kit for the Intel FPGA AI Suite SoC Design Example , saw settings needed on the board and also need to add models & interference graph to the SD card .
Meanwhile I will also check on my end to see whether any known issues or solutions to DLA timeout.
Thanks
Regards
Kian
New ContributorThanks Kian for the response.
Yes, I am following the document steps. Board is setup as per the doc. Model and other required files are generated as per and copied to SD card.
If you get any working image, please share with us so we can check at out end.
