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Honored Contributor
Honored Contributorarria 10 interoperability reference design is not work..!
Hello,
I'm a beginner in FPGA. I'm going to learn the FPGA this year. I want to make a DRFM(Digital Radio Frequency Memory). I follow the document(http://www.alterawiki.com/uploads/3/3c/a10_jesd204b_ad9144_ad9625_ug.pdf) I prepared blow - Arria 10 Development kit - AD9625 EVM, AD 9135 FMC - Windows 7@64bit, 8G RAM, Quartus II 17.0(standard ed.) But example is not working. system log(attached) CONF_DONE pin failed to go high in device 1 . Make use all communication cables are securely connected, .... According to the log, I have changed the device 10AX115S2F45ISG(dev kit.) And then, Start Compilation.. Some errors has occured. ----------------------------------------------------------------------------------------- In fitter(Place & Route) Error# 18757, physical synthesis has been replaced by spectra-q physical synthesis for this device family.. <jesd_204b_ed.qsf> I have modified it. from set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON to comment (#). And re-compilation error occured in EDA Netlist Writer 204012 Can't generate netlist output files because the file... 204009 Can't generate netlist output files because the license for encrypted file... ----------------------------------------------------------------------------------------- The compilation is done. And the output_files is generated. But this is irrelevant. The original in master_file is <jesd_204b_ed.sof> but generated file in output_file is <jesd_204b_ed_time_limited.sof> Anyway, I run the programmer and download it. But it not working. How can I do? --------------------------------------------------------------------------------------------------------------------------------------------- solved.. I had change the Q-sys files.
