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vivekt's avatar
vivekt
Icon for New Contributor rankNew Contributor
5 years ago

ARRIA 10 - REFCLK pins

In the Arria 10 GX FPGA Development Kit. LVDS clock signals are provided to the REFCLK_GXB pins. The clock signals are AC coupled as per the pin connection guide . (Only HCSL can be DC Coupled) Ho...
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
5 years ago

Hi Vivek

You need to enable the OCT in your FPGA design for REFCLK_DP_P/N. The OCT will take care of the Vicm.

Thanks.

Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor
    5 years ago

    Hi Vivek

    We do not receive any response from you to the previous answer that have been provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.

    Eng Wei