New ContributorA simple and gate in verilog is simulated and assigned output pin to 3.3v standard pin in cyclone V 5cgxfc5c6f27cn fpga board and the voltage observed at output pin is 600m volts and not 3.3V .May i know what is the reason for this?
Super ContributorWay more info needed.
What is the FPGA design (source code)? What pin was selected and how was it set up in Pin Planner? Is this a dev kit or a custom board?
Regular ContributorWe sincerely apologize for the inconvenience caused by the delay in addressing your Forum queries. Due to an unexpected back-end issue in our system, your Forum cases, along with others, did not get through as intended. As a result, we have a backlog of cases that we are currently working through one by one.
Please be assured that we are doing everything we can to resolve this issue as quickly as possible. However, this process will take some time, and we kindly ask for your patience and understanding during this period. The cases will be attended by AE shortly.
We appreciate your patience and understanding, and we are committed to providing you with the best support possible.
Thank you for your understanding.
Regular ContributorHi,
Would you happen to have the info that needs to be shared with us to further check your issue?
regards,
Aqid
Regular ContributorI hope the previous response was sufficient to help you proceed. As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.
