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CHung's avatar
CHung
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

AN881 reference design need to be upgraded for device 1SM21CH.

Hi, ​ The following reference design is based on 1SM21BH device. https://fpgacloud.intel.com/devstore/platform/19.1.0/Pro/an881-pcie-avmm-dma-gen3x16-ddr4-and-hbm2/ ​ We use Stratix 10 MX 1SM21C...
BoonT_Intel's avatar
BoonT_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

They are the same, I check the example design in edv kit package. All pin location is compatible.

This this moment, maybe you should signalap the PCIe signal and understand where the problem come from. Example of signal tap signals as below:

CHung's avatar
CHung
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

Hi

​

We have dumped PCIe signalTap waveforms (.jpg and .vcd), please download here:

http://gofile.me/4v7Zs/5QrPiwKwN

​

  1. pcie_reset_trigger
  2. pcie_reset_release
  3. avmm_bridge_512_0_rst_n_release
  4. pcie_idle

​

1, 2, 3 are the waveform around system reset.

4 is the waveform after reset.

Because we are not familiar with PCIe protocol and signals inside IP,

could you please help to analyze them?

It seems clocks and reset signals are OK. But Linux could not recognize it.

Thanks.