Occasional Contributor
Frequent ContributorPlease give it a try with the post-processing again. This is a must step if re-generate the Qsys.
By the way, can I get some clarification from you:-
1. In the screen shot capture you are targeting DDR4, is it expected? In this case, I assume the DDR4 DIMM is slot in to the board right? We need to ensure the DDR4 is calibrated successfully. Can you assign the DDR4 calibration status signal to an indicator like LED or signaltap?
2. Did you change the design like BARs size etc? I assume you direct upgrade the design from BHU to CHU, run the post processing script and did not make any modification right?
If the issue still persist after run the post processing script, is it possible to send the design to mefor review? Thanks
Occasional ContributorHi,
I try the script today, but the result is still the same.
1.
We expect to use both DDR4 and HBM2, but either DDR or HBM2 failed.
And yes, DDR4 DIMM is in the FPGA board.
I think the root cause is related to PCIe gen3x16, not DDR4.
Because PCIe controller didn't sent any request to DDR/HBM according to SignalTap, although Linux can recognize PCIe and BIOS can allocate BAR memory space.
There must be something wrong inside PCIe hard IP+.
i.e. RDDM/WRDM/BAM interface never toggle during testing.
2.
No, we didn't change BAR size. As you said, we only upgrade the design and run script, then start the compilation.
We attach the project files, please review it.
It would be better if you can get a CHU board and trying this design.
I thought Intel should provide a board to you, but I don't know why it's difficult to get a CHU board inside Intel during previous discussion and experiments.
Thank you.
