AN810 saws that the ADC and FPGA clocks need to be run off of the same source, different clocks. Why is this (clock drift, synchronization)? What clock source you used to drive the FPGA clock and the ADC Sample clock?

Hi Tom!

"It is not mandatory for the same SYSREF signal to be generated to all devices in the system. However, it is required that SYSREF signals be generated to all devices in a manner that ensures a deterministic relationship between when SYSREF is sampled active by all devices in the system." from JEDEC Standard No. 204B, Page 31.

Trace matching is a way to get correct timing relationships between SYSREF and ADC clock.

Required setup/hold time for ADC's SYSREF PORT you can see on page 10 ad9208 datasheet (https://www.analog.com/media/en/technical-documentation/data-sheets/ad9208.pdf).

Your system should meet these requirements to avoid problems with correct data transferring from ADC to FPGA.

Design, as you can see in AN810, should be constrained with set_output_delay timing constraints of SYSREF_IO to provide correct setup/hold timing for ADC's ports.

Best regards,

Ivan