AN810 saws that the ADC and FPGA clocks need to be run off of the same source, different clocks. Why is this (clock drift, synchronization)? What clock source you used to drive the FPGA clock and the ADC Sample clock?

Thanks for the reply Ivan.

I looked at the link that you sent and It makes sense that the clock for the ADC and the FPGA need to be on the same frequency reference.

What I am still a little confused about is that the document that you sent says that the SYSREF and the ADC sampling clock need to have matched traces. However in AN810 (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an810.pdf), it shows that the FPGA is providing the SYSREF signal to the ADC board. I assume that the FPGA is providing a signal that is phase matched with the device clock which is synchronized with the ADC sample clock, but in the JESD204B users guide, it shows that the you need to match the traces between the ADC sample clock and the SYSREF clock to prevent phase offset. By using the FPGA to generate the SYSREF and then sending it to the ADC on another SMA cable it seems that you would be introducing more phase delay, which they are trying to prevent. Will this cause any problems or is the ADC not that sensitive to phase offset?

Thanks,

Tom