AN810 saws that the ADC and FPGA clocks need to be run off of the same source, different clocks. Why is this (clock drift, synchronization)? What clock source you used to drive the FPGA clock and the ADC Sample clock?

Hi TKunk1!

AN810 describes the case that's JESD204B standard requirement. Both the ADC and the FPGA must share the same clock. That's JESD204B standart requirement. Refer to"4.4. Clocking Scheme" of JESD204B User Guide for more information (https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_jesd204b.pdf)

I also want to mention that usually there are different ADC dev. boards which have own internal clock source which distribute clocks to both ADC and FPGA, and it that case you don't need an external clock source.

In case of AN810 you should use external clock source for both devices. It could be same source or several sources with phase synchronisation.

Best regards,

Ivan