Altera DE-10-Nano UART Rx and Tx in Pin Planner

Good point dlim!

I have discovered a program utility called System Builder that was shipped with the unit. Basically it generates a Quartus project with the pin declarations that you need and bypass the troubles I had with Pin Planner.

It ended up working correctly and I took some time looking into the generated files.

The below is part of the Verilog file which is generated by the System Builder:you can see the HPS pins being assigned in what is intended to be the top file.

//=======================================================
// This code is generated by Terasic System Builder
//=======================================================
 
module DE10_NANO(
 
	//////////// CLOCK //////////
	input 		     		FPGA_CLK1_50,
	input 		     		FPGA_CLK2_50,
	input 		     		FPGA_CLK3_50,
 
	//////////// HPS //////////
	inout 		     		HPS_CONV_USB_N,
	[...]
	input 		     		HPS_UART_RX,
	output		     		HPS_UART_TX,
	[...]
 
	//////////// KEY //////////
	input 		   [1:0]		KEY,
 
	//////////// LED //////////
	output		   [7:0]		LED,
 
	//////////// SW //////////
	input 		   [3:0]		SW,
 
	//////////// GPIO_1, GPIO connect to GPIO Default //////////
	inout 		  [35:0]		GPIO
);
 
endmodule
 

While in the QSF file you can see the pins being assigned.

#============================================================
# Build by Terasic System Builder
#============================================================
[...]
 
#============================================================
# CLOCK
#============================================================
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK1_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK2_50
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to FPGA_CLK3_50
set_location_assignment PIN_V11 -to FPGA_CLK1_50
set_location_assignment PIN_Y13 -to FPGA_CLK2_50
set_location_assignment PIN_E11 -to FPGA_CLK3_50
 
#============================================================
# HPS
#============================================================
[...]
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_RX
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_UART_TX
[...]
 
#============================================================
# End of pin assignments by Terasic System Builder
#============================================================

Still I'm unsure how I was supposed to know that, but maybe I missed it somewhere in the number of tutorial I checked on the topic.

Thank you again dlim, I appreciated a lot your input!

Iggy