Altera ddr3 UniPHY cyclone-V recovery removal timing issue

Hi

Do you set any global resource for the reset_n_reg signal ?

I am coping the PHY Reset Recovery and Removal guideline from the EMIF handbook. It says you can improve the timing either way.

PHY Reset Recovery and Removal
A common cause for reset timing violations in UniPHY designs is the selection of a global or regional
clock network for a reset signal.
The UniPHY IP does not require any dedicated clock networks for reset signals. Only UniPHY PLL
outputs require clock networks, and any other PHY signal using clock networks may result in timing
violations.
You can correct such timing violations by:
• Setting the Global Signal logic assignment to Off for the problem path (using the Assignment Editor),
or
• Adjusting the logic placement (using the Assignment Editor or Chip Planner)