Altera Cyclone V Development Kit Jumper Postion

Document "ug_cv_soc_dev_kit.pdf" in conjunction with the schematic show the info. E.g. in section 3-2, page 12, there is a diagram and then some tables below it. You can see in the figure that BOOTSEL0 (J28) has a jumper around the two left pins, that is pin 1 and 2. And then below in table 3-4, says for BOOTSEL0, the default position is pins 1 and 2. That confirms that the left two pins are 1 and 2.

Ok, now in the schematic on page 6 on the right side, you can see that pin 1 is pulled high and pin 3 is pulled low, and pin 2 is the signal to the FPGA. So, shorting pins 1 and 2 connects the signal to high.

In summary, left indicates 1, right indicates 2.