[Agilex]:bridge configuration invalid in PCIe
Dear Intel Support Team,
We are encountering a problem in our Agilex SOC Development Kit, which is connected to an I210-T1 Ethernet Server Adapter.
Please find the below prints
[ 0.147739] altera-pcie a0000000.pcie: host bridge /soc/bridge@80000000/pcie@200000000 ranges:
[ 0.147799] altera-pcie a0000000.pcie: MEM 0x0090000000..0x009fffffff -> 0x0000000000
[ 0.147846] altera-pcie a0000000.pcie: port_conf_stat_off =14000
[ 0.148076] altera-pcie a0000000.pcie: PCI host bridge to bus 0000:00
[ 0.148095] pci_bus 0000:00: root bus resource [bus 00-ff]
[ 0.148113] pci_bus 0000:00: root bus resource [mem 0x90000000-0x9fffffff] (bus address [0x00000000-0x0fffffff])
[ 0.148186] pci 0000:00:00.0: [1172:0000] type 01 class 0x060400
[ 0.148257] pci 0000:00:00.0: enabling Extended Tags
[ 0.148406] pci 0000:00:00.0: PME# supported from D0 D3hot
[ 0.149540] pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring
[ 0.149725] pci 0000:01:00.0: working around ROM BAR overlap defect
[ 0.149740] pci 0000:01:00.0: [8086:1533] type 00 class 0x020000
[ 0.149797] pci 0000:01:00.0: reg 0x10: [mem 0x90000000-0x900fffff]
[ 0.149868] pci 0000:01:00.0: reg 0x1c: [mem 0x90000000-0x90003fff]
[ 0.149936] pci 0000:01:00.0: reg 0x30: [mem 0x90000000-0x900fffff pref]
[ 0.150206] pci 0000:01:00.0: PME# supported from D0 D3hot D3cold
[ 0.150642] pci_bus 0000:01: busn_res: [bus 01-ff] end is updated to 01
[ 0.150691] pci 0000:00:00.0: BAR 14: assigned [mem 0x90000000-0x901fffff]
[ 0.150710] pci 0000:00:00.0: BAR 15: assigned [mem 0x90200000-0x902fffff pref]
[ 0.150730] pci 0000:01:00.0: BAR 0: assigned [mem 0x90000000-0x900fffff]
[ 0.150754] pci 0000:01:00.0: BAR 6: assigned [mem 0x90200000-0x902fffff pref]
[ 0.150778] pci 0000:01:00.0: BAR 3: assigned [mem 0x90100000-0x90103fff]
[ 0.150801] pci 0000:00:00.0: PCI bridge to [bus 01]
[ 0.150817] pci 0000:00:00.0: bridge window [mem 0x90000000-0x901fffff]
[ 0.150833] pci 0000:00:00.0: bridge window [mem 0x90200000-0x902fffff pref]
[ 0.150930] pcieport 0000:00:00.0: enabling device (0000 -> 0002)
Thanks & Regards
Satrasala Raju
Hello Raju1421,
Thank you for the update. We have identified that this is more closely related to the FPGA development kits and falls outside the scope of our support.
We will proceed to transfer this thread to the appropriate group to ensure you receive better support accordingly.
Regards,
Irwan_Intel