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veriguy's avatar
veriguy
Icon for Occasional Contributor rankOccasional Contributor
4 years ago
Solved

Agilex F-Series FPGA Dev Kit example design compilation

It looks like the example design supplied with dev-kit "golden_top" has not actually been compiled. There is a typo in the verilog file that causes a syntax error during rtl analysis & synthesis phas...
  • veriguy's avatar
    veriguy
    4 years ago

    Able to compile after removing the transceiver pins from top verilog file as well as qsf file. Missed a pin last time, that is why it was not compiling.

veriguy's avatar
veriguy
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

Hi Eng Wei,

Here I have attached a simple project based on the example design supplied in the dev-kit. I have modified the verilog file to include a simple counter to light up the LEDs in the sequence of numbers. The fitter does not complete due to the error above, so the pin file is not produced. However, the pin assignments are in qsf file. You can simply compile this project to reproduce the error. I used Quartus version 21.1 to compile this.

Thanks

Anshu

EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
4 years ago

Hi Anshu

I don't see the above mentioned errors in the compilation.

The very 1st error I am seeing is as below:

Error(20732): I/O pin "fm6_pcie_perstn~CLUSTER" is a GPIO, but "BU58" has no GPIO resource.

I believe it is due to the pin is not connected to any transceiver logic in the design. Removing assignment on this pin help the compilation to move forward, but hitting a lot of fitter issues due to most of the transceiver pins are not connected. Possible related to this:

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd01022012_343.html

For the errors you mentioned in your initial thread, most likely the IO standard you assigned on those pins are not compatible with the associated banks.

Thanks.

Eng Wei