Forum Discussion
Agilex 5 HSIO Bank Clocks
Good day,
How can a 1.8V clock be connected to the HSIO banks? The Intel Agilex 5 Premium development kit seems to connect a few 1.8V LVDS clocks to HSIO banks powered at 1.1V or 1.2V (VCCIO_PIO). There is a voltage divider (orange block) added to the clock signals, but the resistors seem to be non-populated. However, the resistors are 10kOhm on both sides. Should one not use lower resistor values to not affect the impedance of the LVDS lines?
Should all HSIO pins within a bank not be within a tolerance of the VCCIO_PIO supply of that bank? None of these tolerances will allow for 1.8V LVDS.
Will it be better to add a resistor divider for all LVDS (1.8V) clock pairs to reduce them to 1.1/1.2V? Which resistor values are suggested to avoid losing signal integrity?
Kind regards,
Nicole
4 Replies
- AqidAyman_Altera
Regular Contributor
Hello Nicole,
From Si5332 clock gen datasheet, LVDS spec as below
Vcm = 0.8V
VPP_SE = 0.375V
VPP_SE --> Signal swing at HIGH -> 0.8 + (0.375/2) = 0.9875V.
That should be still within limit of HSIO pin.
- Nicole04
Occasional Contributor
Hi Aqid,
Thank you for your reply. I see what you mean. In the meantime, I set up these 1.8V clocks to be AC coupled and then biased to 1.1V or 1.2V depending on the HSIO bank voltage. Is this a better solution?
Kind regards,
Nicole
- AqidAyman_Altera
Regular Contributor
Hello Nicole,
I apologize as I can't verify the functionalities of your design if it is not following the same as the schematic of the development kit.
If you can confirm the results will be within the limit for the pin, then should be okay.
Regards,
Aqid
- AqidAyman_Altera
Regular Contributor
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