Agilex 5 HSIO Bank Clocks
Good day,
How can a 1.8V clock be connected to the HSIO banks? The Intel Agilex 5 Premium development kit seems to connect a few 1.8V LVDS clocks to HSIO banks powered at 1.1V or 1.2V (VCCIO_PIO). There is a voltage divider (orange block) added to the clock signals, but the resistors seem to be non-populated. However, the resistors are 10kOhm on both sides. Should one not use lower resistor values to not affect the impedance of the LVDS lines?
Should all HSIO pins within a bank not be within a tolerance of the VCCIO_PIO supply of that bank? None of these tolerances will allow for 1.8V LVDS.
Will it be better to add a resistor divider for all LVDS (1.8V) clock pairs to reduce them to 1.1/1.2V? Which resistor values are suggested to avoid losing signal integrity?
Kind regards,
Nicole