Agilex 5 A5ED013B: No legal IOPLL placement with EMIF Calibration IP (Err 16234)

Device: A5ED013BB32AE4SCS

Quartus Prime Pro 25.1.1 Build 125

I am trying to reconfigure a standalone fabric IOPLL at runtime using the EMIF Calibration IP (emif_io96b_cal), following the HSIO reconfiguration flow described in the Clocking and PLL User Guide (813671), section 6.1/6.4, and the approach discussed in this thread:

Agilex 5 reconfigurable PLL - emif | Altera Community - 122952

Setup:

- ps_pll: Intel IOPLL FPGA IP, "Enable dynamic reconfiguration of PLL using Calibration IP" = true, IOPLL Type = "I/O Bank" (only selectable value in the GUI), 50 MHz reference clock.

- EMIF Calibration IP (emif_io96b_cal), INSTANCE_ID = 0, NUM_CALBUS_PLLS = 1, NUM_CALBUS_PERIPHS = 0, AXI4-Lite subordinate port in FABRIC mode.

- pll_calbus / pll_calbus_readdata wired directly between the two IPs.

The Fitter fails during the very first placement/plan stage with:

Error(14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 IOPLL(s)).

Error(175001): The Fitter cannot place 1 IOPLL, which is within IOPLL FPGA IP ps_pll_altera_iopll_2000_ihvozry.

Error(16234): No legal location could be found out of 11 considered location(s).

Error(175005): Could not find a location with: HVIO_IOPLL (6 locations affected)

Error(175008): Location was not in the legal region (5 locations affected)

I isolated this down to a minimal reproduction:

1) A plain, non-reconfigurable IOPLL alone: places fine.

2) The same IOPLL with calbus reconfiguration enabled, standalone (no EMIF IP at all): places fine.

3) The EMIF Calibration IP alone, calbus tied off, unconnected to any PLL: places fine.

4) The reconfigurable IOPLL and EMIF Calibration IP both present in the same design but NOT wired together (calbus tied off independently on each side): places fine.

5) The reconfigurable IOPLL wired to the EMIF Calibration IP via calbus (the actual intended configuration): fails with the error above, 100% reproducible, regardless of I/O pin location assignments (confirmed by removing every pin constraint from the design entirely - identical error, identical 6+5 location breakdown).

I have also tried, with no change to the error:

- Removing all pin location assignments (refclk, PLL outputs, etc.)

- Setting PLL_REFCLK_INPUT_TYPE to NOT_BALANCED on the IOPLL instance

- Quartus Interface Planner tool - "Update Plan" fails immediately with the identical underlying Fitter conflict, before it can even display a plan.

Can someone from Intel/Altera help me understand what is actually driving this placement conflict and how to resolve it? Happy to share the minimal reproduction project if useful.