about Spansion flash

Hi Jake,

simply for test i used the TSE MAC in 10/100 Mhz small MAC mode. I removed the gmii_mii_mux module and modified my top level file. But still I got the error message that "ERROR : MAC Group[0] - No PHY connected!". I am really confused. Any response is appreciated. My top level file is:

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module ddr2_test_top(

enet_rx_dv,

enet_rx_crs,

enet_rx_col,

enet_rx_clk,

enet_tx_clk,

enet_rx_er,

pb_user_resetn,

clk,

enet_rxd,

enet_tx_en,

enet_tx_er,

mdc,

ddr2_cas_n,

ddr2_rasn,

ddr2_wen,

mdio,

ddr2_a,

ddr2_ba,

ddr2_cke,

ddr2_clk_n,

ddr2_clk_p,

ddr2_csn,

ddr2_dm,

ddr2_dq,

ddr2_dqs_p,

ddr2_odt,

enet_txd

);

input enet_rx_dv;

input enet_rx_crs;

input enet_rx_col;

input enet_rx_clk;

input enet_tx_clk;

input enet_rx_er;

input pb_user_resetn;

input clk;

input [3:0] enet_rxd;

output enet_tx_en;

output enet_tx_er;

output mdc;

output ddr2_cas_n;

output ddr2_rasn;

output ddr2_wen;

inout mdio;

output [13:0] ddr2_a;

output [1:0] ddr2_ba;

output [0:0] ddr2_cke;

inout [2:0] ddr2_clk_n;

inout [2:0] ddr2_clk_p;

output [0:0] ddr2_csn;

output [0:0] ddr2_dm;

inout [7:0] ddr2_dq;

inout [0:0] ddr2_dqs_p;

output [0:0] ddr2_odt;

output [3:0] enet_txd;

wire mdio_out;

wire mdio_oen;

assign wire_GND = 0;

assign mdio = mdio_oen ? 1'bz : mdio_out;

nios_ddr2 b2v_inst(.clk_to_tse_pll(clk),

.clk(clk),

.reset_n(pb_user_resetn),

.global_reset_n_to_the_ddr_sdram_0(pb_user_resetn),

.m_rx_col_to_the_tse_mac(enet_rx_col),

.m_rx_crs_to_the_tse_mac(enet_rx_crs),

.m_rx_d_to_the_tse_mac(enet_rxd),

.m_rx_en_to_the_tse_mac(enet_rx_dv),

.m_rx_err_to_the_tse_mac(enet_rx_er),

.mdio_in_to_the_tse_mac(mdio),

.rx_clk_to_the_tse_mac(enet_rx_clk),

.tx_clk_to_the_tse_mac(enet_tx_clk),

.mem_dqs_to_and_from_the_ddr_sdram_0(ddr2_dqs_p),

.mem_clk_n_to_and_from_the_ddr_sdram_0(ddr2_clk_n),

.mem_clk_to_and_from_the_ddr_sdram_0(ddr2_clk_p),

.mem_dq_to_and_from_the_ddr_sdram_0(ddr2_dq),

.mem_cas_n_from_the_ddr_sdram_0(ddr2_cas_n),

.mem_cke_from_the_ddr_sdram_0(ddr2_cke),

.mem_cs_n_from_the_ddr_sdram_0(ddr2_csn),

.mem_dm_from_the_ddr_sdram_0(ddr2_dm),

.mem_odt_from_the_ddr_sdram_0(ddr2_odt),

.mem_ras_n_from_the_ddr_sdram_0(ddr2_rasn),

.mem_we_n_from_the_ddr_sdram_0(ddr2_wen),

.eth_mode_from_the_tse_mac(wire_GND),

.m_tx_en_from_the_tse_mac(enet_tx_en),

.m_tx_err_from_the_tse_mac(enet_tx_er),

.mdc_from_the_tse_mac(mdc),

.mdio_oen_from_the_tse_mac(mdio_oen),

.mdio_out_from_the_tse_mac(mdio_out),

.m_tx_d_from_the_tse_mac(enet_txd),

.mem_addr_from_the_ddr_sdram_0(ddr2_a),

.mem_ba_from_the_ddr_sdram_0(ddr2_ba));

endmodule

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