about Spansion flash

Hi,

My ethernet function still does not work. I get the same kind of error "ERROR : MAC Group[0] - No PHY connected!". What have i done wrong?

My top level file looks like:

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module ddr2_test_top(

enet_rx_dv,

enet_rx_crs,

enet_rx_col,

enet_rx_clk,

enet_tx_clk,

enet_rx_er,

pb_user_resetn,

clk,

enet_rxd,

enet_tx_en,

enet_gtx_clk,

enet_tx_er,

mdc,

ddr2_cas_n,

ddr2_rasn,

ddr2_wen,

mdio,

ddr2_a,

ddr2_ba,

ddr2_cke,

ddr2_clk_n,

ddr2_clk_p,

ddr2_csn,

ddr2_dm,

ddr2_dq,

ddr2_dqs_p,

ddr2_odt,

enet_txd

);

input enet_rx_dv;

input enet_rx_crs;

input enet_rx_col;

input enet_rx_clk;

input enet_tx_clk;

input enet_rx_er;

input pb_user_resetn;

input clk;

input [7:0] enet_rxd;

output enet_tx_en;

output enet_gtx_clk;

output enet_tx_er;

output mdc;

output ddr2_cas_n;

output ddr2_rasn;

output ddr2_wen;

inout mdio;

output [13:0] ddr2_a;

output [1:0] ddr2_ba;

output [0:0] ddr2_cke;

inout [2:0] ddr2_clk_n;

inout [2:0] ddr2_clk_p;

output [0:0] ddr2_csn;

output [0:0] ddr2_dm;

inout [7:0] ddr2_dq;

inout [0:0] ddr2_dqs_p;

output [0:0] ddr2_odt;

output [7:0] enet_txd;

wire SYNTHESIZED_WIRE_0;

wire SYNTHESIZED_WIRE_1;

wire SYNTHESIZED_WIRE_2;

wire SYNTHESIZED_WIRE_3;

wire SYNTHESIZED_WIRE_4;

wire SYNTHESIZED_WIRE_5;

wire SYNTHESIZED_WIRE_6;

wire SYNTHESIZED_WIRE_24;

wire SYNTHESIZED_WIRE_9;

wire [7:0] SYNTHESIZED_WIRE_10;

wire [3:0] SYNTHESIZED_WIRE_11;

wire SYNTHESIZED_WIRE_25;

wire SYNTHESIZED_WIRE_14;

wire SYNTHESIZED_WIRE_15;

wire SYNTHESIZED_WIRE_16;

wire SYNTHESIZED_WIRE_17;

wire SYNTHESIZED_WIRE_18;

wire SYNTHESIZED_WIRE_19;

wire SYNTHESIZED_WIRE_20;

wire SYNTHESIZED_WIRE_21;

wire [7:0] SYNTHESIZED_WIRE_22;

wire [3:0] SYNTHESIZED_WIRE_23;

assign SYNTHESIZED_WIRE_24 = 0;

nios_ddr2 b2v_inst(.clk_to_tse_pll(clk),

.clk(clk),

.reset_n(pb_user_resetn),

.global_reset_n_to_the_ddr_sdram_0(pb_user_resetn),

.gm_rx_dv_to_the_tse_mac(SYNTHESIZED_WIRE_0),

.gm_rx_err_to_the_tse_mac(SYNTHESIZED_WIRE_1),

.m_rx_col_to_the_tse_mac(SYNTHESIZED_WIRE_2),

.m_rx_crs_to_the_tse_mac(SYNTHESIZED_WIRE_3),

.m_rx_en_to_the_tse_mac(SYNTHESIZED_WIRE_4),

.m_rx_err_to_the_tse_mac(SYNTHESIZED_WIRE_5),

.mdio_in_to_the_tse_mac(SYNTHESIZED_WIRE_6),

.rx_clk_to_the_tse_mac(enet_rx_clk),

.set_1000_to_the_tse_mac(SYNTHESIZED_WIRE_24),

.set_10_to_the_tse_mac(SYNTHESIZED_WIRE_24),

.tx_clk_to_the_tse_mac(SYNTHESIZED_WIRE_9),

.mem_dqs_to_and_from_the_ddr_sdram_0(ddr2_dqs_p),

.gm_rx_d_to_the_tse_mac(SYNTHESIZED_WIRE_10),

.m_rx_d_to_the_tse_mac(SYNTHESIZED_WIRE_11),

.mem_clk_n_to_and_from_the_ddr_sdram_0(ddr2_clk_n),

.mem_clk_to_and_from_the_ddr_sdram_0(ddr2_clk_p),

.mem_dq_to_and_from_the_ddr_sdram_0(ddr2_dq),

.tse_pll_c0(SYNTHESIZED_WIRE_14),

.mem_cas_n_from_the_ddr_sdram_0(ddr2_cas_n),

.mem_cke_from_the_ddr_sdram_0(ddr2_cke),

.mem_cs_n_from_the_ddr_sdram_0(ddr2_csn),

.mem_dm_from_the_ddr_sdram_0(ddr2_dm),

.mem_odt_from_the_ddr_sdram_0(ddr2_odt),

.mem_ras_n_from_the_ddr_sdram_0(ddr2_rasn),

.mem_we_n_from_the_ddr_sdram_0(ddr2_wen),

.eth_mode_from_the_tse_mac(SYNTHESIZED_WIRE_21),

.gm_tx_en_from_the_tse_mac(SYNTHESIZED_WIRE_19),

.gm_tx_err_from_the_tse_mac(SYNTHESIZED_WIRE_20),

.m_tx_en_from_the_tse_mac(SYNTHESIZED_WIRE_17),

.m_tx_err_from_the_tse_mac(SYNTHESIZED_WIRE_18),

.mdc_from_the_tse_mac(mdc),

.mdio_oen_from_the_tse_mac(SYNTHESIZED_WIRE_16),

.mdio_out_from_the_tse_mac(SYNTHESIZED_WIRE_15),

.gm_tx_d_from_the_tse_mac(SYNTHESIZED_WIRE_22),

.m_tx_d_from_the_tse_mac(SYNTHESIZED_WIRE_23),

.mem_addr_from_the_ddr_sdram_0(ddr2_a),

.mem_ba_from_the_ddr_sdram_0(ddr2_ba));

gmii_mii_mux b2v_inst1(.reset_rx_clk(SYNTHESIZED_WIRE_25),

.rx_clk(enet_rx_clk),

.phy_rx_col(enet_rx_col),

.phy_rx_crs(enet_rx_crs),

.phy_rx_dv(enet_rx_dv),

.phy_rx_err(enet_rx_er),

.reset_tx_clk(SYNTHESIZED_WIRE_25),

.tx_clk_ref125(SYNTHESIZED_WIRE_14),

.tx_clk(enet_tx_clk),.mdio_out(SYNTHESIZED_WIRE_15),

.mdio_oen(SYNTHESIZED_WIRE_16),

.m_tx_en(SYNTHESIZED_WIRE_17),

.m_tx_err(SYNTHESIZED_WIRE_18),

.gm_tx_en(SYNTHESIZED_WIRE_19),

.gm_tx_err(SYNTHESIZED_WIRE_20),

.eth_mode(SYNTHESIZED_WIRE_21),

.mdio(mdio),

.gm_tx_d(SYNTHESIZED_WIRE_22),

.m_tx_d(SYNTHESIZED_WIRE_23),

.phy_rx_d(enet_rxd),

.tx_clk_mac(SYNTHESIZED_WIRE_9),

.gtx_clk(enet_gtx_clk),

.phy_tx_en(enet_tx_en),

.phy_tx_err(enet_tx_er),

.mdio_in(SYNTHESIZED_WIRE_6),

.m_rx_col(SYNTHESIZED_WIRE_2),

.m_rx_crs(SYNTHESIZED_WIRE_3),

.m_rx_dv(SYNTHESIZED_WIRE_4),

.m_rx_err(SYNTHESIZED_WIRE_5),

.gm_rx_dv(SYNTHESIZED_WIRE_0),

.gm_rx_err(SYNTHESIZED_WIRE_1),

.gm_rx_d(SYNTHESIZED_WIRE_10),

.m_rx_d(SYNTHESIZED_WIRE_11),

.phy_tx_d(enet_txd));

assign SYNTHESIZED_WIRE_25 = ~pb_user_resetn;

endmodule

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