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JET60200's avatar
JET60200
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5 years ago
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A10SOC: "SPI FPGA IP"'s Interrupt Sender is "7", but in linux Device Tree "irqno" set to “26” ？Why

I'm studying an A10SOC FPGA Project from ADI. In the QSYS Designer, there's an "INTEL FPGA SPI IP" module, its IRQ NUMBER set is to "7" (as below picture). And this spi irq connects to "f2h_irq0" ...
  • Isaac_V_Intel's avatar
    Isaac_V_Intel
    5 years ago

    Hello.


    The "26" is because you have the interruption vector with 32 irq, also the irq have the 51 position. So, in the Linux case, you need to make the correct offset for the system understanding.


    Here is how the macro calculate the offset: #define BUTTON_PIO_IRQ (A10_HPS_BUTTON_PIO_IRQ + 51 - 32)


    Best regards,

    Isaac Vazquez.


Isaac_V_Intel's avatar
Isaac_V_Intel
Icon for Contributor rankContributor
5 years ago

Hello.


The "26" is because you have the interruption vector with 32 irq, also the irq have the 51 position. So, in the Linux case, you need to make the correct offset for the system understanding.


Here is how the macro calculate the offset: #define BUTTON_PIO_IRQ (A10_HPS_BUTTON_PIO_IRQ + 51 - 32)


Best regards,

Isaac Vazquez.


  • JET60200's avatar
    JET60200
    Icon for Contributor rankContributor
    5 years ago

    Thanks @Isaac_V_Intel for the answer,

    I search and found there's the explaination as following on rocketboard ,

    " .. It is worth noting that the GIC IRQ computation for FPGA based peripherals is slightly different for A10 SoC. Unlike CV SoC, the A10 SoC requires us to add 51 to the IRQ value reported in the Platform Designer header and then subtract 32 from that value "

    ( https://rocketboards.org/foswiki/Documentation/HOWTOCreateADeviceTree )

    Appreciate your clarification