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1 Reply
- JohnT_Altera
Regular Contributor
Hi,
May I know if the issue is also happening in simulation? Could you share with me the OpenCL code so that I can take a look on the issue?
Hi
用Opencl进行上交所行情解码开发时,遇到访问FPGA内部RAM时,导致该循环II值不为1,从而导致延迟过大
请帮忙分析问题所在,谢谢!
Hi,
May I know if the issue is also happening in simulation? Could you share with me the OpenCL code so that I can take a look on the issue?