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HungLam
New Contributor
New ContributorA10 GX DEV KIT - PCIE to control SPI core ( 3 wire) IP - Regmap
Hi, I am designing an application similar to PCIe to SPI bridge. I used PCIe HIP and SPI ( 3 wire) peripheral. My design used only bar0 and bar4, and I connect bar4 avmm to spi core avms, PCIe bar4...
HungLamNew Contributor
New ContributorHi,
It worked with nios, but now we would like to hook SPI core to PCIe memory map for direct command from host pc.
I figured out that the problem was with avmm addressing. I am trying to understand, since SPI core using 16 bits bus width, but AVMM from PCIe using 32 bits bus width ( or could be 256 bits bus width).
This caused the issue, I am trying to fix it.
Thanks for your answer!
Halotem12New Contributor
New ContributorDid you manged to solve 3 wire spi core connection ?
