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New Contributor5CSEBA2U23C7SN
Frequent ContributorThank you for contacting Intel FPGA Community Forum.
Please be noted that we requires details information to understand further your issue. Please help to answer questions below in order for us to better understand your position.
1. What is the failure rate? What is the failure rate vs. tested sample? Example: 2 out of 100 units.
2. What is the failure symptom? Please elaborate the failure symptom in detail.
3. When did the failure happen? How did you discover the failure?
4. How did you determine the failure? Please elaborate the procedures.
5. Does the failure unit ever working before failure?
Thank you!
Wani
New ContributorPlease find my reply in blue.
1. What is the failure rate? What is the failure rate vs. tested sample? Example: 2 out of 100 units.
- Total defect is 12pcs out of 5272pcs build.
2. What is the failure symptom? Please elaborate the failure symptom in detail.
- It failed under test parameter SHORT NAIL- 3,596 during ICT test.
3. When did the failure happen? How did you discover the failure?
- This failure detected during ICT testing, after debugging they found the IC signal "DIFFIO_TX_B41N/RZQ_0" point with the "GND” point ohm value does not match.
4. How did you determine the failure? Please elaborate the procedures.
- By measuring the resistance value on trace and compare between good board.
5. Does the failure unit ever working before failure?
- ICT testing is our first testing station in process flow and the signal test parameter is first step to check the grounding before power up the board.
Regards
CT
